Field of Invention
The present disclosure relates generally to a NAND flash memory comprising a current sensing page buffer, and a controlling method thereof.
More particularly, the present disclosure relates to a NAND flash memory comprising an improved current sensing page buffer capable of controlling a sensing current more precisely.
Description of Related Art
Among various types of flash memory devices, NAND-type flash memory devices are increasingly used as high capacity data storage media. Each cell of a flash memory can be programmed to store information by trapping charges, e.g., electrons in the cell by exploiting, for example the Fowler-Nordheim tunneling effect. A control gate of a flash memory cell is connected to a word-line of the flash memory, and a voltage may be provided to the control gate through the word-line. A flash memory cell may be a single level memory cell (SLC) capable of storing a single bit, or a multiple level memory cell (MLC) capable of storing multiple bits. In both an SLC and an MLC, the information stored therein is defined by a corresponding threshold voltage of the memory cell.
FIG. 1A is a simplified block diagram of a conventional NAND flash memory device 100. The flash memory device 100 comprises a memory cell array 20, a page buffer block 30, a data input/output circuit 40 and a row decoder 10. The memory cell array 20 is connected to the page buffer block 30 through bit-lines BL and is connected to the row decoder 10 through word-lines WL and other conductive lines. The conductive lines may be, for example, drain selection lines or source selection lines for addressing specific cell strings of the memory cell array. The memory cell array 20 includes a plurality of cell strings, each including a plurality of memory cells. Each memory cell, i.e., the floating gate of each memory cell transistor, may store data transferred from the page buffer block 30 with the control of the row decoder 10, and transfers the stored data to the page buffer block 30 with the control of the row decoder 10. Memory cells are arranged at intersections of the plurality of bit-lines BL and the plurality of word-lines WL, respectively.
The page buffer block 30 may be connected to the memory cell array 20 and to the data input/output circuit 40 through the bit-lines BL. The page buffer block 30 may drive the bit-lines BL during program, read, and erase operations, and may sense the data stored in each memory cell of the memory cell array 20 during the read operation. The data input/output circuit 40 may also exchange data DATA with an external device. The data input/output circuit 40 may transfer write data received from an external device to the page buffer block 30 before a writing operation and may also transfer read data from the memory cell array 20 to the external device. The data input/output circuit 40 may include a data buffer and a column pass gate, which are well known in the art.
The row decoder 10 is connected to the memory cell array 20. The row decoder 10 may select any one of the word-lines WL1 to WLm based on a received external address. The row decoder 10 may also drive the source selection line and the drain selection line of a cell string to which the addressed cells belong to. The row decoder 10 may apply various voltages such as a program voltage, a pass voltage a read voltage, and a ground voltage, to the word-lines WL as may be needed according to an operation mode.
FIG. 1B is an exemplary block diagram of the memory cell array 20 of FIG. 1A.
The block diagram of FIG. 1B is explained herewith for ease of understanding of an exemplary conventional structure of a NAND flash memory, and not for limiting the invention to this specific scheme. For example, a 3D NAND technology may adopt a different scheme than that shown in FIG. 1B.
The memory cell array 20 includes a plurality of blocks 50. Each block 50 includes a plurality of cell strings 60. Each cell string 60 includes a plurality of memory cells in which data is stored. Memory cells are arranged at intersections of the plurality of bit-lines BL0 to BLm and the plurality of word-lines WL0 to WLr+k−1, respectively. Strings can be selected or deselected by a drain selection line, e.g. DSL0, DSLj, and DSLn, and by a source selection line, e.g. SSL0, SSLj, and SSLn. It is understood that the bit-lines BL0 to BLm of the memory cell array 20 are connected to the page buffer block 30 and the word-lines WL, drain selection lines DSL and source selection lines SSL are connected to the row decoder 10.
FIG. 1C shows an exemplary structure of some cell strings and respective memory cells in the memory cell array of FIG. 1B.
Specifically, FIG. 1C shows four cell strings 60. Each cell string 60 includes a plurality of memory cells 70 in which data is stored, e.g., in the floating gates of the memory cells. In the example of FIG. 1C, one cell string 60 includes four memory cells 70 arranged in series, but it should be understood that the number of the memory cells included in a cell string may vary depending on implementation. Memory cells 70 are arranged at intersections of the plurality of bit-lines BL0 and BL1 and the plurality of word-lines WL0 to WL7, respectively. The number of word lines may be different in various embodiments of the memory cell array. Cell strings can be selected or deselected by controlling the drain selection lines, e.g. DSL0 and DSL1, and by controlling the source selection lines, e.g. SSL0 and SSL1. Bit-lines BL0 and BL1 of the memory cell array 20 are connected to the page buffer block 30. Word-lines WL0 to WL7, drain selection lines DSL0 and DSL1 and source selection lines SSL0 and SSL1 are connected to the row decoder 10.
The gate of the drain select transistor DST of each cell string is connected to a drain selection line, e.g., the DSL0 or the DSL1. The gate of the source select transistor SST of each string is connected to a source selection line, e.g., the SSL0 or the SSL1. The source select transistor SST connects each string to a source line SL, and can be switched on or off. In order to couple a specific cell string to its bit-line, a high voltage can be driven to the gates of the SST and DST of the cell string to switch them on. Due to the drain select transistor DST, the source select transistor SST, the source selection line SSL and the drain selection line DSL, specific strings belonging to a same row can be specifically addressed to carry out an operation such as a programming, an erase, and a read operation. The other strings not selected for the operation can be de-coupled from the bit-lines by driving low voltage to the gates of the drain and source select transistors DST and SST of those strings.
Meanwhile, the architecture of NAND memory devices is driven from market requirements towards the introduction of an all-bit-line (ABL) scheme in order to reduce a floating gate to floating gate (FG-to-FG) coupling effect during programming and satisfy large page size needs. The adoption of an ABL scheme has led to the development of a sensing scheme suitable to the concurrent reading of all cells of a physical word-line. A traditional charge integration sensing scheme, also known as “voltage sensing”, required the alternate reading of cells connected to even and odd bit-lines so as to provide bit-line to bit-line shielding by grounding unselected bit-lines. A recent sensing scheme, known as “current sensing,” provides a reliable reading of even and, odd bit-lines at the same time, thus requiring a single reading step for both. The current sensing scheme provides the advantage of reading all cells of a physical word-line at the same time and thus effectively doubling the page size. According to the current sensing scheme, it is also possible to verify all cells of a word-line concurrently, which also improves program performance, both in throughput and reliability. Moreover, since all cells of a word-line are programmed in parallel, the cell to cell interference is minimized. As a drawback, the current sensing scheme generally adopted in existing ABL architectures causes a less efficient control of the read current and a greater variation on the parameters which have to be tightly controlled to ensure a wider read margin between distributions.
FIG. 2 shows a conventional page buffer circuit 30 suitable to perform a current sensing operation according to the current sensing scheme.
The page buffer 30 comprises a first node CSO and a sensing node SEN. The bit-line BL extends to the memory cell array 20. A first transistor M1 is arranged between the first node CSO and the bit-line BL. The first transistor M1 is configured to pre-charge the bit-line BL based on a voltage PB_SENSE, more specifically with voltage PB_SENSE minus a gate-source threshold voltage of the first transistor M1. A second transistor M2 is configured to prevent the voltage level of the first node CSO from being lower that the voltage level of SA_CSOC minus a gate-source threshold voltage of the second transistor M2. A third transistor M3 is arranged between the first node CSO and the sensing node SEN. The third transistor M3 connects the first node CSO with the sensing node SEN.
The operation of the page buffer circuit 30 will be explained in reference to FIGS. 2 and 3. FIG. 3 shows a timing diagram of the page buffer circuit 30 performing the current sensing operation. One cycle of the current sensing operation comprises six periods, i.e., a pre-charging period t1, a first evaluation period t2, a first strobe period t3, a recovery period t4, a second evaluation period t5, and a second strobe period t6.
In the pre-charging period t1, firstly, a sense latch 31 is reset so that a node QS has a low voltage level, and then all bit-lines BLs are pre-charged at the same time by raising voltage PB_SENSE to the desired bit-line level plus the gate-source threshold voltage of the first transistor M1. A pre-charge path is powered through third and seventh transistors M3 and M7. The seventh transistor M7 is coupled between the sense node SEN and the drain of a sixth transistor M6 the source of which s coupled to a voltage terminal VCORE. The gate of the sixth transistor M6 is coupled to the QS node. Voltages SA_PRECH and SA_SENSE which are provided to the gates of the third and seventh transistors M3 and M7, respectively, are set to at least the level of a power supply voltage VDC_PB plus a threshold voltage VTH. At the same time, a second transistor M2 gated by a voltage SA_CSOC is enabled by raising a gate voltage SA_CSOC to a level higher than the PB_SENSE voltage. For, example, the SA_CSOC may be raised to 1.4V when the PB_SENSE voltage is set to 1.2V. These voltages are applied for the pre-charging period t1 which is sufficient to pre-charge the bit-lines. Also, the first node CSO and the sensing node SEN, which are connected together by switching on the third transistor M3, are pre-charged to the source voltage VCORE. The source voltage VCORE is usually equal to the power supply voltage VDC_PB, but the two voltages are provided by a separate voltage source. During the pre-charging period t1, voltages applied to an addressed word-line WL and the drain and source selection lines DSL and SSL are raised to ensure the conductive path from an addressed bit-line BL to the source line SL depending on cell status.
Just before the first evaluation period t2, a transistor M11 is disabled by lowering the level of voltage SA_DISCH. The first evaluation period t2 starts when the voltage SA_PRECH is grounded. If the addressed cell is erased, the first node CSO and the sensing node SEN are eventually discharged by a current sunk from the addressed cell. The sensing node SEN and the first node CSO are coupled due to high voltage SA_SENSE driven to the third transistor M3 during the first evaluation period t2.
In the first evaluation period t2, the voltage SA_CSOC of the second transistor M2 ensures that the first node CSO is not discharged below initial bit-line voltage plus a delta by charges provided from the voltage source VCORE. Therefore, the voltage level of bit-line BL is kept constant, which allows bit-line to bit-line interference to be suppressed.
After the first evaluation period t2, strobe signals SA_STB_N and SA_ST are enabled in the first strobe period t3. If the first node CSO and the sensing node SEN have been discharged enough by the cell current, a sensing transistor M5 is enabled and the voltage level of the node QS goes high, otherwise data of the sense latch 31 is maintained. If the voltage level of the node QS goes high, it switches off a transistor M6, and current path from the voltage source VCORE to the bit-line BL is blocked, which results in discharge of the bit-lines through the transistor M11 during the recovery period t4. If the voltage level of the node QS is maintained at its original level, i.e. a low level, the transistor M6 is maintained as switched-on and the voltage path from the voltage source VCORE to the bit-line BL maintains the voltage level of the bit-line.
When the first strobe period t3 ends, the recovery period t4 starts. In the recovery period t4, the voltages SA_CSOC and PB_SENSE are raised to have a higher level (e.g. +0.2V), and the voltages SA_PRECH and SA_DISCH are reasserted. Depending on the value on the sense latch 31, some bit-lines read as “erased” are discharged due to the switched-off transistor M6 and current path established through the transistor M11, and all the other bit-lines read as “not erased” are pre-charged again. After the recovery period t4, operations are performed for more precise reading during the second evaluation period t5 and the second strobe period t6.
At the first evaluation period t2, a source bouncing can be high due to a huge current sunk by strongly erased cells. Slightly erased cells, which should be identified as erased but still having in the floating gates thereof more electrons than the strongly erased cells, can be influenced by the high source bouncing caused by strongly erased cells; thereby the conductive path from the bit-line to the source line SL can be blocked for those slightly erased cells. At the second evaluation period t5, the bit-lines for the cells read as erased in the first evaluation period t2 has been already discharged, which results in a low source bouncing. The low source bouncing allows more precise current sensing operations for the remaining cells.
In the page buffer circuit 300, a read current Itrip for each cell is determined as follows. Since the first node CSO and the sensing node SEN were pre-charged to the level of the voltage source VCORE, the minimum cell current to switch the sensing latch 31 is determined by the following equation 1.
                                                        Itrip              =                            ⁢                                                                    (                                                                                            V                                                      CSO                            ⁢                            _                                                                          ⁢                        precharge                                            -                                                                        V                                                      CSO                            ⁢                            _                                                                          ⁢                        strobe                                                              )                                    *                                ⁢                                                      C                    CSO                                    /                                      T                    eval                                                                                                                          =                            ⁢                                                (                                      VCORE                    -                                          (                                              VDC_PB                        -                        Vth_M5                                            )                                                        )                                *                                                                                                      ⁢                                                                    C                    CSO                                    /                                      T                    eval                                                  ⁢                                  ∼                                ⁢                                  Vth_M5                  *                                ⁢                                                      C                    CSO                                    /                                      T                    eval                                                                                                          [                  Equation          ⁢                                          ⁢          1                ]            
In equation 1, VCSO_precharge represents a final voltage level of the first node CSO in the pre-charging period t1. VCSO_strobe represents the voltage level of the first node CSO in the strobe period t3. CCSO represents a parasitic capacitance of the first node CSO and the sensing node SEN coupled together during the read operation. Teval represents a time for evaluation between a falling edge of the voltage SA_PRECH and a rising edge of a voltage SA STB_N, which is sum of the first evaluation period t2 and the first strobe period t3.
Equation 1 takes into account that, in order to turn the sensing transistor M5 on, the first node CSO should be discharged as much as a threshold voltage of the sensing transistor M5, which is the PMOS transistor, during the time for evaluation. Thus, VCSO_strobe is equal to or less than the power supply voltage VDC_PB minus the source-gate threshold voltage Vth_M5 of the sensing transistor M5 to turn the sensing transistor M5 on.
If it is assumed that the voltage source VCORE equals the power supply voltage VDC_PB, the read current Itrip becomes a function of the source-gate threshold voltage Vth_M5 of the sensing transistor M5. The threshold voltage of a transistor is a function of process parameters and temperature, which is not easily controllable.
Another factor to be considered is that, during the first read operation periods t1 to t3, the current sunk from fully erased cells in parallel could cause a drop on the path from the voltage source VCORE and the page buffer of the other cell. In this case, even if it is assumed that the voltage source VCORE equals the power supply voltage VDC_PB, there will be an actual difference between the voltage source VCORE and the power supply voltage VDC_PB. This difference would affect the equation 1 and additionally cause a variation of the read current Itrip depending on the pattern programmed on the cells of a same word-line.